1. Field of the Invention
The present invention relates to a MOS (Metal-Oxide Semiconductor) transistor and a method for manufacturing the same, and in particular, a high-voltage-resistant MOS transistor having LDD (Lightly Doped Drain) structures and a method for manufacturing the same.
2. Description of the Related Art
A semiconductor device such as a MOS FET having LDD structures is presently known. The LDD structures are formed as lightly doped regions with a dopant concentration lower than that of source and drain regions for the purpose of suppressing electrical field at the drain region and prevent degradation of the drain region. By forming the lightly doped regions in the semiconductor device, it is attempted to manufacture the semiconductor device having high-voltage-resistance.
In a high-voltage resistant offset MOS transistor having a LDD structure, an electrical strength and an on-resistance are dependent upon the length of a lightly doped region referred to as a LDD length. A method for manufacturing a semiconductor device, whose LDD length can be arbitrarily designed, is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 2002-289845 (document D1).
However, in the method disclosed in document D1, it is difficult to eliminate a photolithography process and an ion implantation process for forming lightly doped regions. Such steps increase the number of processes and a processing period for forming the semiconductor device, thus increasing the cost of production.
In addition, in the conventional MOS transistor, there arises a problem that lightly doped diffusion regions can not be formed on the basis of a predetermined electrical strength. The conventional MOS transistor, whose LDD length is arbitrarily configured, also has a problem that photolithographic process can not be eliminated at the time of ion implantation for forming lightly doped diffusion regions and that the ion implantation is required to be performed at least twice.